A personal computer or a workstation has a memory unit for storing data. A DRAM (Dynamic Random-Access Memory) is a kind of memory that allows a large amount of data to be read out from it and written thereto. A DRAM is used as a main memory unit in a personal computer and a workstation.
In addition, a thin-film SOI-MOS transistor has characteristics such as a capability of carrying out operations at high speeds and low powers, improved endurance against radioactive rays, a reduced short-channel effect, a capability of performing operations at high temperatures and manufacturability at high densities. The SOI-transistor is therefore expected to be able to serve as a device structure appropriate for subsequent generations of 1 Gbyte DRAM (G=109) and DRAMs.
FIG. 58 is a simplified sectional view of a memory-cell portion of the conventional SOI-DRAM disclosed in documents such as Symposium on VLSI Technology Digest of Technical Papers, Pages 141 to 142, authored by F. Morishita et al. in the year of 1995. The SOI-DRAM comprises an insulating layer 1 made of a silicon oxide and a silicon layer 2 formed on the insulating layer 1. In addition, the SOI-DRAM also includes a thin-film SOI-MOS transistor 3 formed on the silicon layer 2. The thin-film SOI-MOS transistor 3 comprises a first source/drain 3a including an n+ region 3aa and an n- region 3ab having an impurity concentration lower than the n+ region 3aa, a second source/drain 3b including an n+ region 3ba and an n- region 3bb having an impurity concentration lower than the n+ region 3ba, a body 3c sandwiched by the first source/drain 3a and the second source/drain 3b, a gate oxidation film 3d formed on the body 3c and a gate 3e provided to face the body 3c through the gate oxidation film 3d and a side-wall oxidation film 3f formed on a side wall of the gate 3e.
A substrate with a silicon layer formed on an insulation layer as described above is called an SOI substrate, whereas a MOS transistor made of a thin silicon layer above the insulation layer is called an SOI-MOS transistor. The SOI-DRAM further includes a capacitor 4 connected to the second source/drain 3b of the thin-film SOI-MOS transistor 3. Each memory cell comprises the thin-film SOI-MOS transistor 3 and the capacitor 4.
In the case of the SOI-DRAM with a configuration described above, in a state wherein data is retained in a memory cell, that is, in a state wherein the thin-film SOI-MOS transistor 3 is non-conductive and the capacitor 4 is put at a potential Vsn representing data retained in it, majority carriers are accumulated in a bottom unit 3g of the floating body 3c, raising the potential of the body 3c. As a result, a threshold leak current flowing from the second source/drain 3b to the first source/drain 3a increases in magnitude, eventually giving rise to a problem that the data accumulated in the memory cell is lost at an accelerated pace. The increase in body potential is much dependent upon a reverse bias leak current of PN junctions between the first source/drain 3a, the second source/drain 3b and the body 3c of the thin-film SOI-MOS transistor 3. The difficulty to improve the characteristics of these PN junctions is a problem which remains to be solved.
FIG. 59 is a simplified plane view of an active region in which the thin-film SOI-MOS transistor is made. The active region which includes the first source/drain 3a, the second source/drain 3b and the body 3c is enclosed by an inter-element insulation film 5 separating the active region from other adjacent active regions which are not shown in the figure. In order to prevent majority carriers from being accumulated in the body 3c, a trial was made to take a design of the body 3c into consideration wherein the region of the body 3c is bent to form a shape resembling the L character as shown in the figure. In this design, a ground or negative potential is provided to the body 3c through a contact hole 3ca so as to prevent the body 3c from being put in a floating state. However, a region for providing such a potential is required. Even when such a region is small in comparison with one thin-film SOI-MOS transistor, in the entire DRAM which includes 1 G (1 G=109) pieces of thin-film SOI-MOS transistors, the regions give rise to a problem that a large total surface occupied by the regions entails an increased layout area.